Speed control and speed setting circuits for universal motors are known in which adjustable timing means are connected to the control electrode of the controllable switch means of the speed setting circuit. The adjustable timing means operate under external adjustment to set the speed of the motor at a selected speed at a predetermined load. The control is achieved by varying the phase angle during the alternate half waves at which the controllable switch means become conductive. In the known circuit described in U.S. Pat. No. 3 553 556 the speed control circuit also comprises controllable switch means having a main conductive circuit connected between the AC voltage supply and the motor which, during the half wave during which it is operative, furnishes a second current to the motor which varies in dependence on the value of current in the previous half wave in such a manner that the speed of the motor tends to remain constant, independent of load. In the known system a single capacitor forms part of the timing circuit associated with both the speed control and the speed setting circuits. This has the disadvantage that residual charge retained across the capacitor at the end of the control half wave will affect the speed setting circuit such that the speed setting circuit can only be adjusted to a minimum speed which substantially exceeds zero. A continuous adjustment of motor speed from a predetermined top speed to zero motor speed is thus impossible with the known system.